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rev. 1.4 10/06 copyright ? 2006 by silicon laboratories aero aero a ero ? t ransceiver for gsm and gprs w ireless c ommunications features applications description the aero ? transceiver is a complete rf front end for multi-band gsm and gprs wireless communications. the transmit section interfaces between the baseband processor and the power amplifier. the receive section interfaces between the rf band-select saw filters and the baseband processor. no external if saw filter or vco modules are required as all functions are completely implemented on-chip, resulting in a dramatic reduction of board area and component count. functional block diagram low-if receiver: dual or triple-band lna image-reject down-converter high-performance a/d converters universal baseband interface: digital if to baseband converter, channel-select filter and gain control analog or digital i/q interface offset-pll transmitter: high precision i/q up-converter integrated tx vco and loop filter dual rf synthesizer: integrated rf and if vcos, loop filters, varactors, and resonators quad-band support: gsm 850 class 4, small ms e-gsm 900 class 4, small ms dcs 1800 class 1 pcs 1900 class 1 gprs class 12 compliant cmos process technology low profile packages: si4200: 5 x 5 mm qfn32 si4201: 4 x 4 mm qfn20 si4133t: 5 x 5 mm qfn28 3-wire serial interface 2.7 v to 3.0 v operation multi-band gsm/gprs di gital cellular handsets gsm/gprs wireless data modems adc adc pga pga lna lna lna si4200 if pll rf pll si4133t pa pa gsm dcs pcs gsm dcs pcs 0 / 90 antenna switch det baseband dac dac pga pga channel filter 100 khz si4201 i q i q afc vc-tcxo 13 or 26 mhz xin xout patents pending pin assignments (top view) si4200-g-gm (si4200db-bm see page 41) si4201-bm SI4133T-BM ordering information: see page 44. gnd pad 1 2 3 25 26 27 28 29 30 31 32 ion iop txqn txqp ckn ckp txin txip iflop iflon gnd rflop rflon vdd diag2 diag1 vdd pdn gnd nc nc gnd vdd rfog rfidp rfidn rfipp rfipn rfigp rfign vdd rfod 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8 gnd pad 1 2 3 16 17 18 19 20 gnd rxqp rxqn rxip rxin vdd xin gnd ckp ckn vdd xout sdi sclk sen iop ion xen pdn sdo 11 12 13 14 15 6 7 8 9 10 4 5 gnd pad 1 2 3 22 23 24 25 26 27 28 gnd iflb xin gnd ifla gnd vdd gnd pdn sdo sen sclk sdi gnd vdd iflop iflon vdd rflop rflon gnd rflc gnd gnd rfld rflb rfla gnd 15 16 17 18 19 20 21 8 9 10 11 12 13 14 4 5 6 7
aero 2 rev. 1.4
aero rev. 1.4 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1. receive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2. transmit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3. frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4. vco inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5. serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.6. xout buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 6. pin descriptions: si4200-g- gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7. pin descriptions: si4200db-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8. pin descriptions: si4201-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9. pin descriptions: SI4133T-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 10. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11. package outline: si4200-g- gm and si4200db-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 12. package outline: si4201-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13. package outline: SI4133T-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
aero 4 rev. 1.4 1. electrical specifications table 1. recommended operating conditions 1,2 parameter symbol test condition min typ max unit ambient temperature t a ?202585c dc supply voltage v dd 2.7 2.85 3.0 v dc supply voltages difference v ?0.3 ? 0.3 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at 2.85 v and an o perating temperature of 25 c unless otherwise stated. parameters are tested in production unless otherwise stated. 2. dc supply voltage difference specificatio n applies to power supply pins per ic. table 2. absolute maximum ratings 1,2 parameter symbol value unit dc supply voltage v dd ?0.5 to 3.3 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v dd + 0.3) v operating temperature t op ?40 to 95 c storage temperature t stg ?55 to 150 c rf input level 4 10 dbm notes: 1. permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the si4200 and si4133t devices are high-performance rf integrated circuits with an esd rating of < 2 kv. handling and assembly of these devices should only be done at esd-protected workstations. 3. for signals sclk, sdi, sen , pdn , xen, and xin. 4. at saw filter output for all bands.
aero rev. 1.4 5 table 3. dc characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit si4200 supply current i rx0 receive mode ? 55 80 ma i tx0 transmit mode ? 60 80 ma i pdn0 pdn = 0 ? 1 50 a si4201 supply current 1 i rx1 receive mode ? 9 12 ma i pdn1 pdn = 0, xen = 0, xbuf = 0, xpd1 = 1 ?150a i xout1 pdn = 0, xen = 1 ? 1 2 ma si4133t supply current 2 i rx3 receive mode ? 16 19 ma i tx3 transmit mode ? 22 27 ma i pdn3 pdn = 0 ? 1 50 a total chipset supply current i rx receive mode ? 80 ? ma i tx transmit mode ? 82 ? ma high level input voltage 3 v ih 0.7 v dd ?? v low level input voltage 3 v il ? ? 0.3 v dd v high level input current 3 i ih v ih = v dd = 3.0 v ?10 ? 10 a low level input current 3 i il v il = 0 v, v dd = 3.0 v ?10 ? 10 a high level output voltage 4 v oh i oh = ?500 a v dd ?0.4 ? ? v low level output voltage 4 v ol i ol = 500 a ? ? 0.4 v high level output voltage 5 v oh i oh = ?10 ma v dd ?0.4 ? ? v low level output voltage 5 v ol i ol = 10 ma ? ? 0.4 v notes: 1. measured with load on xout pin of 10 pf and f ref = 13 mhz. limits with xen = 1 guaranteed by characterization. 2. rf1 vco is used for receive mode, rf2 and if vcos are used for transmit mode. center frequencies for each vco are as follows: rf1 = 1.9 ghz, rf2 = 1.35 ghz, if = 825 mhz. 3. for pins sclk, sdi, sen , xen, and pdn . 4. for pins sdo, xout. 5. for pins diag1, diag2.
aero 6 rev. 1.4 figure 1. sclk timing diagram table 4. ac characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk cycle time t clk figure 1, 3 35 ? ? ns sclk rise time t r figure 1, 3 ? ? 50 ns sclk fall time t f figure 1, 3 ? ? 50 ns sclk high time t hi figure 1, 3 10 ? ? ns sclk low time t lo figure 1, 3 10 ? ? ns pdn rise time t pr figure 2 ? ? 10 ns pdn fall time t pf figure 2 ? ? 10 ns sdi setup time to sclk t su figure 3 15 ? ? ns sdi hold time from sclk t hold figure 3 10 ? ? ns sen to sclk delay time t en1 figure 3 10 ? ? ns sclk to sen delay time t en2 figure 3, 4 12 ? ? ns sen to sclk delay time t en3 figure 3, 4 12 ? ? ns sen pulse width t w figure 3, 4 10 ? ? ns sclk to sdo time t ca figure 4 ? ? 27 ns digital input pin capacitance 1 ?? 5 pf allowable board capacitance 2 ?? 1 pf xin input resistance 3 r xin 20 30 40 k xin input capacitance 3 c xin 3.5 5 7 pf xin input sensitivity 3 v ref 0.5 ? ? v pp xin input frequency 3,4 f ref xsel = 0, div2 = 0 ? 13 ? mhz xsel = 1, div2 = 1 ? 26 ? mhz notes: 1. for pins sclk, sdi, sen , xen, and pdn . 2. for pins ckn, ckp, ion, and iop. 3. for xin pins (si4133t pin 7 and si4201 pin 7). 4. the xsel bit controls an internal divide-by-two circuit on the si4201 and does not affect the xout pin. the div2 bit controls an internal divide-by-two circuit on the si4133t. sclk 80% 20% 50% t r t f t lo t clk t hi
aero rev. 1.4 7 figure 2. pdn timing diagram figure 3. serial interface write timing diagram figure 4. serial interface read timing diagram pdn 80% 20% t pr t pf t en1 80% 50% 20% 80% 50% 20% 80% 50% 20% d17 d16 a0 t r t w t en2 t f t lo t hi t clk t hold t su sdi sclk sen t en3 80% 50% 20% 80% 50% 20% 80% 50% 20% a0 80% 50% 20% sdi sclk sen sdo od17 od0 od16 t ca t en2 t en3 t w
aero 8 rev. 1.4 table 5. receiver characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit gsm input frequency 1 f in gsm 850 band 869 ? 894 mhz e-gsm 900 band 925 ? 960 mhz dcs or pcs input frequency 1 dcs 1800 band 1805 ? 1880 mhz pcs 1900 band 1930 ? 1990 mhz noise figure at 25 c 2,3 nf 25 gsm 850 band ? 2.6 3.3 db e-gsm 900 band ? 2.7 3.4 db dcs 1800 band ? 3.2 3.9 db pcs 1900 band ? 3.6 4.3 db noise figure at 75 c 2,3 nf 75 gsm 850 band ? 3.3 4.0 db e-gsm 900 band ? 3.4 4.1 db dcs 1800 band ? 4.1 4.8 db pcs 1900 band ? 4.8 5.5 db noise figure at 85 c 2,3 nf 85 gsm 850 band ? 3.4 4.1 db e-gsm 900 band ? 3.5 4.2 db dcs 1800 band ? 4.5 5.2 db pcs 1900 band ? 5.1 5.8 db 3 mhz input desensitization 2,3,4 des 3 gsm input ?25 ?21 ? dbm dcs / pcs inputs ?28 ?25 ? dbm 20 mhz input desensitization 2,3,4 des 20 gsm input ?20 ?16 ? dbm dcs / pcs inputs ?19 ?15 ? dbm input ip2 2 ip2 |f 1,2 ? f 0 | 6 mhz, |f 2 ? f 1 | = 100 khz 29 40 ? dbm input ip3 2 ip3 |f 2 ? f 1 | 800 khz, f 0 = 2f 1 ? f 2 ?18 ?12 ? dbm image rejection 2 ir gsm input 28 35 ? db dcs / pcs inputs 28 40 ? db 1 db input compression 2,5 cp max gsm input ?28 ?23 ? dbm dcs / pcs inputs ?27 ?22 ? dbm 1 db input compression 2,6 cp min gsm input ?23 ?18 ? dbm dcs / pcs inputs ?23 ?18 ? dbm minimum voltage gain 2,6,7 g min gsm input 4.5 8.5 12.5 db dcs / pcs inputs 11.5 15.5 19.5 db maximum voltage gain 2,7 g max gsm input 100 104 108 db dcs / pcs inputs 96 102 106 db
aero rev. 1.4 9 lna voltage gain 3,8 g lna gsm input ? 17 ? db dcs / pcs inputs ? 15 ? db lna gain control range g lna gsm input 131721db dcs / pcs inputs 4 8 12 db analog pga control range g apga 13 16 19 db analog pga step size 3.2 4.0 4.8 db digital pga control range g dpga ?63?db digital pga step size ? 1 ? db maximum differentia l output voltage 9 dacfs[1:0] = 00 0.8 1.0 1.2 v ppd dacfs[1:0] = 01 1.6 2.0 2.4 v ppd dacfs[1:0] = 10 2.8 3.5 4.2 v ppd output common mode voltage 9 daccm[1:0] = 00 0.8 1.0 1.2 v daccm[1:0] = 01 1.05 1.25 1.45 v daccm[1:0] = 10 1.15 1.35 1.55 v differential output offset voltage 9,10 ??50mv baseband gain error 9,10 ?? 1 % baseband phase error 10,11 ?? 1deg output load resistance 10 r l single-ended 10 ? ? k output load capacitance 10 c l single-ended ? ? 10 pf group delay 11 csel = 0 ? ? 22 s csel = 1 ? ? 16 s differential group delay 11 csel = 0 ? ? 1.5 s csel = 1 ? ? 1 s powerup settling time 3,12 from powerdown ? 200 220 s table 5. receiver characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
aero 10 rev. 1.4 notes: 1. gsm input pins rfigp and rfign. dcs input pins rfidp and rfidn. pcs input pins rfipp and rfipn. on the si4200db, the pcs input pins should be used for either pcs 1900 or dcs 1800 bands. 2. measurement is performed with a 2:1 balun (50 input, 200 balanced output) and includes matching network and pcb losses. measured at max gain (again[2:0] =max=100 b , lnag[1:0] = max=01 b , lnac[1:0] = max=01 b ) unless otherwise noted. noise figure measurements are refe rred to 290 k. insertion loss of the balun is removed. 3. specifications are guaranteed by characterization. 4. wanted signal at balun input is ?102 dbm. snr at baseband output is 9 db. 5. again[2:0]=min=000 b , lnag[1:0] = max=01 b , lnac[1:0] =max= 01 b . 6. again[2:0]=min=000 b , lnag[1:0] = min=00 b , lnac[1:0] = min=00 b . 7. voltage gain is defined as the differential rms voltage at the rxip/rxin pins or rxqp/rxqn pins divided by the rms voltage at the balun input with dacfs[ 1:0] = 01 and csel = 1. gain is 1.5 db higher with csel = 0. minimum and maximum values do not include the variation in the si4201 dac full scale voltage (also see maximum differential output voltage specification). 8. voltage gain is defined as the differential rms voltage at the lna output divided by the rms voltage at the balun output. 9. output pins rxip, rxin, rxqp, rxqn. 10. the baseband signal path is entirely digital. gain, phase , and offset errors at the bas eband outputs are because of the si4201 d/a converters. offsets can be measured and calibr ated out. see zerodel[2:0] in the register description. 11. group delay is measured from antenna input to baseba nd outputs. differential group delay is measured in-band. 12. includes settling time of the si4133t frequency synthesizer. settling to 5 degrees phase error measured at rxip, rxin, rxqp, and rxqn pins. table 5. receiver characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
aero rev. 1.4 11 figure 5. receive path magnitude response (csel = 0) figure 6. receive path passband magnitude response (csel = 0) figure 7. receive path passband group delay (csel = 0) 0 50 100 150 200 250 300 350 400 ?120 ?100 ?80 ?60 ?40 ?20 0 receive path magnitude response (csel = 0) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 receive path passband magnitude response (csel = 0) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 15 16 17 18 19 20 21 22 23 24 25 receive path passband group delay (csel = 0) group delay (usec) frequency (khz)
aero 12 rev. 1.4 figure 8. receive path magnitude response (csel = 1) figure 9. receive path passband magnitude response (csel = 1) figure 10. receive path passband group delay (csel = 1) 0 50 100 150 200 250 300 350 400 ?80 ?60 ?40 ?20 0 receive path magnitude response (csel = 1) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 receive path passband magnitude response (csel = 1) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 10 11 12 13 14 15 16 17 18 19 20 receive path passband group delay (csel = 1) group delay (usec) frequency (khz)
aero rev. 1.4 13 table 6. transmitter characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit rfog output frequency 1 gsm 850 band 824 ? 849 mhz e-gsm 900 band 880 ? 915 mhz rfod output frequency 2 dcs 1800 band 1710 ? 1785 mhz pcs 1900 band 1850 ? 1910 mhz i/q differential input swing 3,4 0.88 ? 2.2 v ppd i/q input common-mode 3 1.1 ? 1.4 v i/q differential input resistance 3,4 bbg[1:0] = 11 b 26 30 35 k bbg[1:0] = 00 b 22 25 29 k bbg[1:0] = 01 b 17 20 23 k powered down ? hi-z ? k i/q input capacitance 3,5 ?? 5 pf i/q input bias current 3 13 16 19 a sideband suppression 67.7 khz sinusoid ? ?46 ?34 dbc carrier suppression 67.7 k hz sinusoid ? ?48 ?33 dbc im3 suppression 67.7 khz sinusoid ? ?57 ?50 dbc phase error 5 ?1.93.0 o rms ?510 o peak txvco pushing 1,2 open loop ? 100 ? khz/v txvco pulling 1,2 vswr 2:1, all phases, open loop ?200?khz pp rfog output modulation spectrum 1,6 400 khz offset ? ?65 ?63 dbc 1.8 mhz offset ? ?70 ?68 dbc rfod output modulation spectrum 2,6 400 khz offset ? ?65 ?63 dbc 1.8 mhz offset ? ?70 ?65 dbc rfog output phase noise 1,5,7 10 mhz offset ? ?160 ?155 dbc/hz 20 mhz offset ? ?166 ?164 dbc/hz rfod output phase noise 2,5,7 20 mhz offset ? ?163 ?157 dbc/hz rfog output power level 1 z l = 50 7911dbm rfod output power level 2 z l = 50 6810dbm rf output harmonic suppression 1,2 2nd harmonic ? ? ?20 dbc 3rd harmonic ? ? ?10 dbc
aero 14 rev. 1.4 powerup settling time 5,8 from powerdown ? ? 150 s notes: 1. measured at rfog pin. 2. measured at rfod pin. 3. input pins txip, txin, txqp, and txqn. 4. differential input swing is programmable with the bbg[1:0] bi ts in register 04h. program these bits to the closest appropriate value. the i/q input resistance scales inversely with the bbg[1:0] setting. 5. specifications are guaran teed by characterization. 6. measured with pseudo-random pattern. carrier power and noise power < 1.8 mhz measured with 30 khz rbw. noise power 1.8 mhz measured with 100 khz rbw. 7. measured with all 1s pattern. 8. includes settling time of the si4133t frequency synthesizer. se ttling time measured at the rfod and rfog pins to 0.1 ppm frequency error. table 6. transmitter characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
aero rev. 1.4 15 table 7. frequency synthesizer characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit rf1 vco frequency 1 f rf1 gsm 850 band 1737.8 ? 1787.8 mhz e-gsm 900 band 1849.8 ? 1919.8 mhz dcs 1800 band 1804.9 ? 1879.9 mhz pcs 1900 band 1929.9 ? 1989.9 mhz rf2 vco frequency 1 f rf2 gsm 850 band 1272 ? 1297 mhz e-gsm 900 1279 ? 1314 mhz dcs 1800 band 1327 ? 1402 mhz pcs 1900 band 1423 ? 1483 mhz if vco frequency 1 f if gsm 850 band ? 896 ? mhz e-gsm 900 band 880?895 mhz 900?915 mhz ?798?mhz e-gsm 900 band 895?900 mhz ?790?mhz dcs 1800 band ? 766 ? mhz pcs 1900 band ? 854 ? mhz rf1 pll phase detector update frequency f gsm input, rfup = 0 ?200?khz dcs/pcs inputs, rfup = 1 ?100?khz if and rf2 pll phase detector update frequency f ?200?khz rf1 vco nominal capacitance 2,3 c nom ?4.3? pf rf2 vco nominal capacitance 2,3 ?4.8? pf if vco nominal capacitance 2,3 ?6.5? pf rf1 vco package inductance 2,3 l pkg ?1.5?nh rf2 vco package inductance 2,3 ?1.5?nh if vco package inductance 2,3 ?1.6?nh rf1 vco pushing 3 open loop ? 500 ? khz/v rf2 vco pushing 3 ?400?khz/v if vco pushing 3 ?300?khz/v
aero 16 rev. 1.4 rf1 vco pulling 3 vswr = 2:1, all phases, open loop ?400?khz pp rf2 vco pulling 3 ?100?khz pp if vco pulling 3 ?100?khz pp rf1 pll phase noise 3 3 mhz offset ? ?144 ?138 dbc/hz rf2 pll phase noise 3 400 khz offset ? ?126 ?121 dbc/hz if pll phase noise 3 400 khz offset ? ?128 ?123 dbc/hz rf1 pll spurious 3 3 mhz offset ? ?95 ?83 dbc rf2 pll spurious 3 400 khz offset ? ?80 ?75 dbc if pll spurious 3 400 khz offset ? ?80 ?70 dbc notes: 1. for the gsm input, the rf1 vco is divided by two on the si 4200. during transmit, the if vco is divided by two on the si4200. these tuning ranges are guarant eed provided the vcos on the si4133t are properly centered during the pc board design phase. see ?an49: aero transceiv er pcb layout guidelines ? for more information. 2. see ?4.4. vco inductor design? on page 23.. 3. specifications are guaran teed by characterization. table 7. frequency synthesizer characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
aero rev. 1.4 17 2. typical application schematic figure 11. typical triple-band application circuit notes: 1. connect gnd pad on bottom of u1?u3 to gnd. 2. all vdd pins may be fed from a single supply or regulator. 3. for dual-band designs, the dcs lna input pins (u1 pins 19?20) should be grounded. for a complete pinout, see "7. pin descriptions: si4200db-bm" on page 41. 4. see ?an49: aero transceiver pcb layout guidelines? for details on the following: lna matching network (c1?c6, l1?l3). values should be cust om tuned for a specific pcb layout and saw filter to optimize performance. differential traces between the saw filter s (z1?z3) and transceiver (u1) pins 17?22. detailed saw filter requirements. l4 and pcb inductor traces l5?l6 for frequency synthesizer (u3) pins 2?3, 16?17 and 19?20. ckp/ckn and iop/ion differential traces between transcei ver (u1) pins 1?4 and baseband interface (u2) pins 9?12. dcs rx input rxqp pcs rx input sdi egsm rx input txqp xout txin sclk sdo rxin rxip rxqn txip sen pdn txqn dcs/pcs tx output egsm tx output xin vdd vdd vdd vdd vdd vdd 3 v vdd vdd c9 l1 l2 c1 u1 si4200 28 7 3 4 5 6 8 9 10 12 13 14 15 20 19 18 17 16 22 21 25 24 23 11 27 26 1 2 29 30 31 32 nc txqp ckn ckp txip txin txqn iflop iflon rflop rflon vdd diag2 rfidn rfidp rfipn rfipp diag1 rfign rfigp rfog rfod vdd gnd gnd vdd ion iop nc gnd pdn vdd u2 si4201 1 2 3 4 5 6 7 9 10 11 15 14 13 12 8 16 17 18 19 20 gnd rxqp rxqn rxip rxin vdd xin ckp ckn iop sdo pdn xen ion gnd sen sclk sdi xout vdd u3 si4133t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gnd iflb ifla gnd vdd gnd xin gnd pdn sdo sen sclk sdi gnd gnd rfld rflc gnd rflb rfla gnd gnd rflon rflop vdd iflon iflop vdd z1 out+ out- in gnd l3 z2 out+ out- in gnd z3 out+ out- in gnd c14 c2 c6 c5 c3 c4 l5 l6 c8 c13 c11 c12 c10 l4 c7 xen r1
aero 18 rev. 1.4 3. bill of materials component(s) value/description supplier(s) c1?c2 1.2 pf, 0.1 pf, c0g (gsm 850 and e-gsm 900) murata grm36c0g series venkel c0402c0g500 series c3?c4 1.0 pf, 0.1 pf, c0g (dcs 1800) murata grm36c0g series venkel c0402c0g500 series c5?c6 1.0 pf, 0.1 pf, c0g (pcs 1900) murata grm36c0g series venkel c0402c0g500 series c7?c8 100 pf, 5%, c0g venkel c0402c0g500-101jne c9, c10, c13, c14 22 nf, 20%, z5u c11, c12 10 pf, 20%, c0g murata grp1555c1h100jz01 venkel c0402c0g500-100jnb l1 24 nh, 5% murata lqw18an series (0603 size) murata lqw15a series (0402 size) l2 7.5 nh, 0.5 nh murata lqw18an series (0603 size) murata lqw15a series (0402 size) l3 6.8 nh, 0.2 nh murata lqw18an series (0603 size) murata lqw15a series (0402 size) l4 3.9 nh, 5% multi-layer (0402 or 0603 size) l5 inductor for rf1 vco pcb trace l6 inductor for rf2 vco pcb trace r1 100 , 5% u1 gsm transceiver silicon laboratories si4200-bm u2 universal baseband interfac e silicon laborato ries si4201-bm u3 rf synthesizer silicon l aboratories SI4133T-BM z1 gsm 850 rx saw filter (150 or 200 balanced output) epcos b39881-b7719-c610 (6-pin, 2.0x2.5 mm) epcos b39881-b9001-c710 (5-pin, 1.4x2.0 mm) murata safsd881mfl0t00r00 (6-pin, 2.0x2.5 mm) murata safek881mfl0t00r00 (6-pin, 1.6x2.0 mm) e-gsm 900 rx saw filter (150 or 200 balanced output) epcos b39941-b7721-c910 (6-pin, 2.0x2.5 mm) epcos b39941-b7820-c710 (5-pin, 1.4x2.0 mm) murata safsd942mfm0t00r00 (6-pin, 2.0x2.5 mm) murata safek942mfm0t00r00 (6-pin, 1.6x2.0 mm) z2 dcs 1800 rx saw filter (150 or 200 balanced output) epcos b39182-b7749-c910 (6-pin, 2.0x2.5 mm) epcos b39182-b7821-c710 (5-pin, 1.4x2.0 mm) murata safsd1g84fa0t00r00 (6-pin, 2.0x2.5 mm) murata safek1g84fa0t00r00 (6-pin, 1.6x2.0 mm) z3 pcs 1900 rx saw filter (150 or 200 balanced output) epcos b39202-b7741-c910 (6-pin, 2.0x2.5 mm) epcos b39202-b7825-c710 (5-pin, 1.4x2.0 mm) murata safsd1g96fb0t00r00 (6-pin, 2.0x2.5 mm) murata safek1g96fa0t00r00 (6-pin, 1.6x2.0 mm)
aero rev. 1.4 19 4. functional description figure 12. aero transceiver block diagram the aero transceiver is the industry?s most integrated rf front end for multi-band gsm/gprs digital cellular handsets and wireless data modems. the chipset consists of the si4200 gsm transceiver, si4201 universal baseband interface, and si4133t dual rf synthesizer. the highly inte grated solution eliminates the if saw filter, external low noise amplifiers (lnas) for three bands, transmit and rf voltage controlled oscillator (vco) modules, and more than 60 other discrete components found in conventional designs. the high level of integration combined with quad flat no- lead package (qfn) technology and fine line cmos process technology results in a solution with 50% less area and 80% fewer components than competing solutions. a triple-band gsm transceiver using the aero chipset can be implemented with 24 components in less than 2.4 cm 2 of board area. this level of in tegration is an enabling force in lowering the cost, simplifying the design and manufacturing, and shrinking the form factor in next-generation gsm/gprs voice and data terminals. the receive section uses a digital low-if architecture that avoids the difficulti es associated with direct conversion while deliveri ng lower solution cost and reduced complexity. the universal baseband interface is compatible with any s upplier?s baseband subsystem. the transmit section is a complete up-conversion path from the baseband subsystem to the power amplifier, and uses an offset phase locked loop (pll) with a fully integrated transmit vco. the frequency synthesizer uses silicon laboratories? proven technology, which includes integrated rf and if vcos, varactors, and loop filters. the unique integer-n pll architecture used in the si4133t produces a transient response that is superior in speed to fractional-n architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. this fast transient response makes the aero ch ipset well suited to gprs multi-slot applications where channel switching and settling times are critical. while conventional solutions use bicmos or other bipolar process technologies, the aero chipset is the industry?s first cellular tran sceiver to be implemented in a 100% cmos process. this brings the cost savings and extensive manufacturing capacity of cmos to the gsm market. adc adc pga pga lna lna lna si4200 if pll rf pll si4133t pa pa gsm dcs pcs gsm pcs dcs 0 / 90 antenna switch det baseband dac dac pga pga channel filter 100 khz si4201 i q i q afc vc-tcxo 13 or 26 mhz xin xout
aero 20 rev. 1.4 4.1. receive section figure 13. receiver block diagram the aero transceiver uses a low-if receiver architecture that allows for the on-chip integration of the channel selection filters, eliminating the external rf image reject filters and the if saw filter required in conventional superheterodyne architectures. compared to a direct- conversion architecture, the low-if architecture has a much greater degree of immunity to dc offsets that can arise from rf local oscillat or (rflo) self-mixing, 2nd- order distortion of blockers, and device 1/f noise. this relaxes the common-mode balance requirements on the input saw filters and simplifies pc board design and manufacturing. the si4200 integrates three differential-input lnas. the gsm input supports the gsm 850 (869?894 mhz) or e- gsm 900 (925?960 mhz) bands. the dcs input supports the dcs 1800 (1805?1880 mhz) band. the pcs input supports the pcs 1900 (1930?1990 mhz) band. for quad-band designs, saw filters for the gsm 850 and e-gsm 900 bands should be connected to a balanced combiner that drives the gsm input for both bands. for dual-band designs using the si4200db-bm, the pcs input should be used for either dcs 1800 or pcs 1900 bands. the lna inputs are matched to the 150 or 200 balanced-output saw filters through external lc matching networks. see ?an49: aero transceiver pcb layout guidelines? for implementation details. the lna gain is controlled with the lnag[1:0] and lnac[1:0] bits in register 05h. a quadrature image-reject mixer downconverts the rf signal to a 100 khz intermediate frequency (if) with the rflo from the si4133t frequency synthesizer. the rflo frequency is between 1737.8 and 1989.9 mhz, and is divided by two in the si4200 for gsm 850 and e- gsm 900 modes. the mixer output is amplified with an analog programmable gain amplifier (pga), which is controlled with the again[2:0] bits in register 05h. the quadrature if signal is digitized with high resolution a/d converters (adcs). the si4201 downconverts the adc output to baseband with a digital 100 khz quadrature lo signal. digital decimation and iir filters perform channel selection to remove blocking and reference interference signals. the response of the iir filter is programmable to a high selectivity setting (csel = 0) or a low selectivity setting (csel = 1). the low selectivit y filter has a flatter group delay response that may be desirable where the final channelization filter is in the baseband chip. after channel selection, the digital output is scaled with a digital pga, which is contro lled with the dgain[5:0] bits in register 05h. the lnag[1:0], lnac[1:0], again[2:0] and dgain[5:0] bits must be set to provide a constant amplitude signal to the baseband receive inputs. see ?an51: aero transceiver agc strategy? for more details. dacs drive a differential analog signal onto the rxip, rxin, rxqp and rxqn pins to interface to standard analog-input baseband ics. no special processing is required in the baseband for offset compensation or extended dynamic range. the receive and transmit baseband i/q pins can be mult iplexed together into a 4- wire interface. the common mode level at the receive i and q outputs is programmable with the daccm[1:0] bits, and the full scale level is programmable with the dacfs[1:0] bits in register 12h. baseband dac dac pga pga channel filter 100 khz adc adc pga pga lna lna lna si4200 0 / 90 si4133t si4201 i q rf pll n rf1 [15:0] rfup rxband[1:0] lnac[1:0] lnag[1:0] again[2:0] csel dgain[5:0] daccm[1:0] dacfs[1:0] zerodel[2:0] pcs dcs gsm
aero rev. 1.4 21 4.2. transmit section figure 14. transmitter block diagram the transmit (tx) section consists of an i/q baseband upconverter, an offset phase-locked loop (opll) and two output buffers that can drive external power amplifiers (pa), one for the gsm 850 (824 to 849 mhz) and e-gsm 900 (880 to 915 mhz) bands and one for the dcs 1800 (1710 to 1785 mhz) and pcs 1900 (1850 to 1910 mhz) bands. the opll requires no external filtering to attenuate transmitter noise or spurious signals in the receive band, saving both cost and power. additionally, the output of the transmit vco (txvco) is a constant-envelope signal which reduces the problem of spectral spreading caused by non- linearity in the pa. a quadrature mixer upconverts the differential in-phase (txip, txin) and quadrature (txqp, txqn) signals with the iflo to generate a ssb if signal which is filtered and used as the reference input to the opll. the si4133t generates the iflo frequency between 766 and 896 mhz. the iflo is divided by two to generate the quadrature lo signals for the quadrature modulator, resulting in an if between 383 and 448 mhz. for the e-gsm 900 band, two different iflo frequencies are required for spur management. therefore, the if pll must be programmed per channel in the e-gsm 900 band. the iflo frequencies are defined in table 7 on page 15. the opll consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated txvco. the txvco is centered between the dcs 1800 and pcs 1900 bands, and its output is divided by two for the gsm 850 and e-gsm 900 bands. the si4133t generates the rflo frequency between 1272 and 1483 mhz. to allow a single vco to be used for the rflo, high-side injection is used for the gsm 850 and e-gsm 900 bands, and low-si de injection is used for the dcs 1800 and pcs 1900 bands. the i and q signals are automatically swapped within the si4200 when switching bands. additionally, the swap bit in register 03h can be used to manually exchange the i and q signals. low-pass filters before the opll phase detector reduce the harmonic content of the quadrature modulator and feedback mixer outputs. the cutoff frequency of the filters is programmable with th e fif[3:0] bits in register 04h and should be set to the recommended settings detailed in the register description. baseband det pa pa i q gsm dcs pcs if pll rf pll si4133t 2 fif[3:0] n rf2 [15:0] pdrb n if [15:0] pdib 1, 2 txband[1:0] si4200 reg reg bbg[1:0] swap
aero 22 rev. 1.4 4.3. frequency synthesizer figure 15. si4133t frequency synthesizer block diagram the si4133t dual frequency synthesizer is a monolithic cmos integrated circuit that performs if and rf synthesis. two complete plls are integrated including vcos, varactors, resonators, loop filters, reference and vco dividers, and phase detectors. differential outputs for the if and rf plls are provided for direct connection to the si4200 transceiver ic. the rf pll uses two multiplexed vcos. the rf1 vco is used for receive mode, and the rf2 vco is used for transmit mode. the if pll is used only during transmit mode. the if and rf output frequencies are set by programming the n-divider registers, n rf1 , n rf2 , and n if . programming the n-divider register for either rf1 or rf2 automatically selects the proper vco. the output frequency of each pll is as follows: the div2 bit in register 31h controls a programmable divider at the xin pin to allow either a 13 or 26 mhz reference frequency. for receive mode, the rf1 pll phase detector update rate (f ) should be programmed to f = 100 khz for dcs 1800 or pcs 1900 bands, and to f = 200 khz for gsm 850 and e-gsm 900 bands. for transmit mode, the rf2 and if pll phase detector update rates are always f =200khz. si4133t self tune det rf1 rf2 n n rf1 [15:0] n rf2 [15:0] 65, 130 1, 2 power control serial i/o n det n if [15:0] rfup div2 pdib pdrb sdosel[4:0] if pll rf pll self tune rflc, rfld rfla, rflb iflb ifla rflop rflon iflop iflon sen sclk sdo sdi pdn xin f out nf =
aero rev. 1.4 23 4.4. vco inductor design figure 16. vco block diagram 4.4.1. determining l ext the center frequencies for t he rf1, rf2, and if vcos in the si4133t are set using an external inductance (l ext ). it is very important that l ext be properly designed to ensure maximum manufacturing margin for the desired vco frequency tuning ranges. because the total tank inductance is in the low nh range, the inductance of the package (l pkg ) must be considered in determining the correct external inductance. figure 16 shows the detailed configuration of the integrated vcos. the total inductance (l tot ) of each vco is the sum of the external inductance (l ext ) and the package inductance (l pkg ). the total capacitance (c tot ) of each vco is the sum of the self tuning capacitance (c tune ), the pll varactor capacitance (c var ), and the fixed capacitance (c fix ). the nominal capacitance (c nom ) of each vco is calculated with c tune and c var at their center values. c nom and l pkg values are defined in table 7. the center frequency is calculated as follows: the value for the external inductor is determined by: where f cen = desired center frequency of vco c nom = nominal capacitance from table 7. l pkg = package inductance from table 7. l ext = external inductance required for example, the rf1 vco for a triple-band design requires f cen = 1897 mhz. table 7 on page 15 shows c nom = 4.3 pf and l pkg = 1.5 nh for the rf1 vco. the above equation shows l ext = 0.14 nh should be connected between the rfla and rflb pins. please see ?an49: aero transceiver pcb layout guidelines? for details on how to implement and verify the proper value of l ext . package board ic pll self tune amp c var c tune c fix l ext l pkg /2 l pkg /2 si4133t f cen 1 2 c nom l pkg l ext + () ------------------------------------------------------------------- = l ext 1 2 f cen () 2 c nom ------------------------------------------- - l pkg ? = table 8. vco f cen values (mhz) supported bands rf1 vco rf2 vco if vco european dual-band (900/1800) 1862 1341 782 triple-band (900/1800/1900) 1897 1381 810 quad-band (850/900/1800/1900) or north american dual band (850/1900) 1864 1378 831 table 9. vco l ext values (nh) supported bands rf1 vco rf2 vco if vco european dual-band (900/1800) 0.20 1.43 4.77 triple-band (900/1800/1900) 0.14 1.27 4.34 quad-band (850/900/1800/1900) or north american dual band (850/1900) 0.20 1.28 4.04
aero 24 rev. 1.4 4.5. serial interface a three-wire serial interfac e is provided to allow an external system controller to write the control registers for dividers, receive path gain, powerdown settings, and other controls. the serial control word is 24 bits in length, comprised of an 18-b it data field and a 6-bit address field as shown in figure 17. a single logical register space is shared among the three chips, which is summarized in table 10 on page 25. figure 17. serial interface format the serial interface pins are intended to be connected in parallel to both the si4201 and the si4133t. serial control is relayed from the si4201 to the si4200 over the signal interface (iop/ion and ckp/ckn pins). all registers must be written when the pdn pin is asserted (low), except for register 22 h. all serial interface pins should be held at a constant level during receive and transmit bursts to minimize spurious emissions. this includes stopping the sclk clock. a timing diagram for the serial interface is shown in figure 3 on page 7. when the serial interface is enabled (i.e., when sen is low), data and address bits on the sdi pin are clocked into an internal shift register on the rising edge of sclk. data in the shift register is then transferred on the rising edge of sen into the internal data register addressed in the address field. the internal shift register ignores any leading bits before the 24 required bits. the serial interface is disabled when sen is high. optionally, registers can be read as illustrated in figure 4 on page 7. the serial output data appears on the sdo pin after writing the revision register with the address to be read. sdo is enabled when pdn =0 on the si4201 and when pdn = 1 on the si4133t, allowing the sdo pin to be shared. writing to any of the registers causes the function of sdo to revert to its previously programmed function. 4.6. xout buffer the si4201 contains a reference clock buffer to drive the baseband input. the clock signal from the vc- tcxo is capacitively coupled to the xin pin on the si4201. the clock signal is not divided with the xsel control. the xout buffer is a cmos driver stage with approximately 250 of series resistance. this buffer is enabled when the xen hardware control (pin 13 on the si4201) is set high, independent of the pdn control pin. to achieve complete powerdown during sleep, the xen pin must be set low, the xbuf bit in register 12 must be set to zero, and the xpd1 bit in register 11 must be set to one. during normal operation, these bits should set to their default values. d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 5 a 4 a 3 a 2 a 1 a 0 data field address field last bit clocked in d 16 d 17
aero rev. 1.4 25 5. control registers notes: 1. any register not listed here is reserved and should not be written. writing to reserved register s may result in unpredictable behavior. 2. master registers 20h to 24h simplify programming the aero tm transceiver to support initiation of receive (rx) and transmit (tx) operations wit h only two register writes. 3. see ?an50: aero transceiver programming guide? for detailed instructions on register programming. table 10. register summary reg name bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00h si4200 revision/read 0000000000 rev0[7:0] 01h reset 00000000000000000r eset 02h mode 000000000000000automode[1:0] 03h config 0 0 0 0 diag[1:0] swap 0 0 0 txband[1:0] rxband[1:0] 0 0 1 0 04htransmit 00000001bbg[1:0] fif[3:0] 000 0 05h receive 0 0 0 0 dgain[5:0] 0 again[2:0] lnac[1:0] lnag[1:0] 10h si4201 revision/read 0000000000 rev1[7:0] 11h config 0000 dpds[2:0] xpd11xsel0101000csel 12hdac config00000001xbuf0zdbszerodel[2:0]daccm[1:0]dacfs[1:0] 19hreserved 00000000000000000 0 master registers 20h rx master #1 rxband[1:0] n rf1 [15:0] 21h rx master #2 0 dpds[2:0] lnac[1:0] lnag[1:0] again[2:0] 0 dgain[5:0] 22hrx master #3000000000000 dgain[5:0] 23h tx master #1 txband[1:0] n rf2 [15:0] 24h tx master #2 fif[3:0] n if [13:0] 30h si4133t revision/read 0000000000 rev3[7:0] 31h config 000 sdosel[3:0] 000000rfupdiv200 1 32hpowerdown0000000000000000pdibpdrb 33h rf1 n divider 0 0 n rf1 [15:0] 34h rf2 n divider 0 0 n rf2 [15:0] 35h if n divider 0 0 n if [15:0] 3ahreserved 00000000000000100 1 3ehreserved 00000000000000111 1 3fhreserved 00000000000001000 0
aero 26 rev. 1.4 note: registers on the si4200 can be read by writing this r egister with the address of the register to be read. register 00h. revision/read (si4200) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000 rev0[7:0] bit name function 17:8 reserved read as zero. 7:0 rev0[7:0] si4200 revision (read only). 00h = si4200 revision a 01h = si4200 revision b 02h = si4200 revision c 03h = si4200 revision d 14h = si4200db revision e (dual-band) 05h = si4200 revision f (triple-band) register 01h. reset (si4200/si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name 00000000000000000r eset bit name function 17:1 reserved program to zero. 0 reset chip reset. 0 = normal operation (default). 1 = reset all registers to default values. note: see ?5. control registers? on page 25. for more details. this register must be written to 0 twice after a reset operation. this bit does not reset si4133t registers 30h to 35h.
aero rev. 1.4 27 note: calibration must be performed each time the power suppl y is applied. to initiate the calibration mode, set mode[1:0] = 10, and pulse the pdn pin high for at least 150 s. register 02h. mode control (si4200/si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000000automode[1:0] bit name function 17:3 reserved program to zero. 2auto automatic mode select. 0 = manual. mode is controlled by mode[1:0] bits (default). 1 = automatic. last register write to n rf1 implies rx mode; last register write to n rf2 implies tx mode. mode [1:0] bits are ignored. 1:0 mode[1:0] transmit/receive/calibration mode select. 00 = receive mode (default). 01 = transmit mode. 10 = calibration mode. 11 = reserved. note: these bits are valid only when auto = 0.
aero 28 rev. 1.4 register 03h. configuration (si4200) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000diag[1:0]swap000txband[1:0]rxband[1:0]0010 bit name function 17:14 reserved program to zero. 13:12 diag[1:0] diag1/diag2 ou tput select. diag1 diag2 00 = low low (default) 01 = low high 10 = high low 11 = high high note: these pins can be used to control antenna switch functions. these bits must be programmed with the pdn pin is zero. the diag1/diag2 pins are be held at the desired value regardless of the state of the pdn pin. 11 swap transmit i/q swap. 0 = normal (default). 1 = swap i and q for txip, txin, txqp and txqn pins. 10:8 reserved program to zero. 7:6 txband[1:0] transmit band select. 00 = gsm 850 or e-gsm 900 (default). 01 = dcs 1800. 10 = pcs 1900. 11 = reserved. 5:4 rxband[1:0] receive band select. 00 = gsm input. (default), 01 = dcs input. 10 = pcs input. 11 = reserved. 3:2 reserved program to zero. 1 reserved program to one. 0 reserved program to zero.
aero rev. 1.4 29 register 04h. transmit control (si4200) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000001 bbg[1:0] fif[3:0] 0000 bit name function 17:11 reserved program to zero. 10 reserved program to one. 9:8 bbg[1:0] tx baseband input full scale differential input voltage. 10 = reserved. 11 = 2.0 v ppd . 00 = 1.7 v ppd (default). 01 = 1.3 v ppd . note: refer to table 6 for minimum and maximum values. set this register to the nearest value. 7:4 fif[3:0] tx if filter cutoff frequency. 0111 = use for gsm 850, e-gsm 900 and pcs 1900 bands. 0110 = use for dcs 1800 band. note: use the recommended setting for each band. other settings reserved. 3:0 reserved program to zero.
aero 30 rev. 1.4 register 05h. receive gain (si4200/si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 0 0 0 dgain[5:0] 0 again[2:0] lnac[1:0] lnag[1:0] bit name function 17:14 reserved program to zero. 13:8 dgain[5:0] digital pga gain control. 00h = 0 db (default). 01h = 1 db. ... 3fh = 63 db. note: see ?an51: aero transceiver agc strategy? for details on setting the gain registers. 7 reserved program to zero. 6:4 again[2:0] analog pga gain control. 000 = 0 db (default). 001 = 4 db. 010 = 8 db. 011 = 12 db. 100 = 16 db. 101 = reserved. 110 = reserved. 111 = reserved. note: see ?an51: aero transceiver agc strategy? for details on setting the gain registers. 3:2 lnac[1:0] lna bias current control. 00 = minimum current (default). 01 = maximum current. 10 = reserved. 11 = reserved. note: program these bits to the same value as same as lnag[1:0] 1:0 lnag[1:0] lna gain control. 00 = minimum gain (default). 01 = maximum gain. 10 = reserved. 11 = reserved. notes: 1. program these bits to the same value as same as lnac[1:0] 2. see ?an51: aero transceiver agc strategy? for details on setting the gain registers.
aero rev. 1.4 31 note: registers on the si4201 can be read by writing this r egister with the address of the register to be read. register 10h. revision/read (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000 rev1[7:0] bit name function 17:8 reserved read as zero. 7:0 rev1[7:0] si4201 revision (read only). 00h = rev a. 01h = rev b. 02h = rev c (latest version).
aero 32 rev. 1.4 register 11h. configuration (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 0 0 0 dpds[2:0] xpd1 1 xsel 0 1 0 1 0 0 0 csel bit name function 17:14 reserved program to zero. 13:11 dpds[2:0] data path delayed start. 111= use for gsm 850 and gsm 900 bands. 011= use for dcs 1800 and pcs 1900 bands (default). note: use the recommended setting for each band. other settings reserved. 10 xpd1 reference buffer powerdown. 0 = reference buffer automatically enabled (default). 1 = reference buffer disabled. note: this bit should be set to 0 during normal operation. to achieve lowest si4201 powerdown current (i pdn1 ), this bit should be set to 1. the xbuf bit in register 12h must also be set appropriately. 9 reserved program to one. 8 xsel reference frequency select. 0 = no divider. xin = 13 mhz (default). 1 = divide xin by 2. xin = 26 mhz. note: the internal clock should always be 13 mhz. 7 reserved program to zero. 6 reserved program to one. 5 reserved program to zero. 4 reserved program to one. 3:1 reserved program to zero. 0csel digital iir coef ficient select. 0 = high selectivity filter (default). 1 = low selectivity filter.
aero rev. 1.4 33 register 12h. dac configuration (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 0 0 0 0 0 0 1 xbuf 0 zdbs zerodel[2:0] daccm[1:0] dacfs[1:0] bit name function 17:11 reserved program to zero. 10 reserved program to one. 9 xbuf reference buffer power control. 0 = reference buffer disabled. 1 = reference buffer automatically enabled (default). note: this bit should be set to 1 during normal operation. to achieve the lowest si4201 power down current (i pdn1 ), this bit should be set to 0. the xpd1 bit in register 11h must also be set appropriately. 8 reserved program to zero. 7zdbs zerodel band select. 0 = use zerodel[2:0] settings co rresponding to dcs/pcs column (default). 1 = use rxband[1:0] to determine zerodel[2:0] dela y setting (gsm or dcs/pcs). 6:4 zerodel[2:0] rx output zero delay. code gsm dcs/pcs 000: 90 s 130 s(default) 001: 110 s150 s 010: 130 s170 s 011: 140 s180 s 100: 150 s190 s 101: 160 s200 s 110: 180 s220 s 111: reserved note: dac input is forced to zero after pdn is deasserted. this feature can be used for baseband adc offset calibration. offsets induced on channels due to 13 mhz harmonics are not included in the calibrated value. 3:2 daccm[1:0] rx output common mode voltage. 00 = 1.0 v. 01 = 1.25 v (default). 10 = 1.35 v. 11 = reserved. 1:0 dacfs[1:0] rx output differential full scale voltage. 00 = 1.0 v ppd . 01 = 2.0 v ppd (default). 10 = 3.5 v ppd . 11 = reserved.
aero 34 rev. 1.4 notes: 1. see registers 03h and 33h for bit definitions. 2. when this register is written, th e pdib bit automatically sets to 0, the pdrb bi t is set to 1, and the rfup bit is set as a function of rxband[1:0]. note: see registers 05h and 11h for bit definitions. notes: 1. see register 05h for bit definitions. 2. the dgain[5:0] in register 22h c an be changed without powering down. register 19h. reserved (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000000000 bit name function 17:0 reserved program to zero. register 20h. rx master #1 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name rxband[1:0] n rf1 [15:0] register 21h. rx master #2 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 dpds[2:0] lnac[1:0] lnag[1:0] again[2:0] 0 dgain[5:0] register 22h. rx master #3 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000000000 0 dgain[5:0]
aero rev. 1.4 35 notes: 1. see registers 03h and 34h for bit definitions. 2. when this register is written, th e pdib bit automatically sets to 1, and the pdrb bit is set to 1. note: see registers 04h and 35h for bit definitions. note: registers on the si4133t can be read by writing this re gister with the address of the register to be read. register 23h. tx master #1 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name txband[1:0] n rf2 [15:0] register 24h. tx master #2 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name fif[3:0] n if [13:0] register 30h. revision/read (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000 rev3[7:0] bit name function 17:8 reserved read as zero. 7:0 rev3[7:0] si4133t revision (read only). 80h = rev a. 81h = rev b. 82h = rev c (latest revision).
aero 36 rev. 1.4 register 31h. main configuration (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000 sdosel[3:0] 000000rfupdiv2001 bit name function 17:15 reserved program to zero. 14:11 sdosel[3:0] sdo output control register. the mux_output table is as follows: 0000 connected to the output shift register (default). 0001 force the output to low. 0010 reference clock. 0011 lock detect (ldetb) signal from phase detectors. 1111 high impedance. notes: 1. sdo is high-impedance when pdn = 0. 2. sdo is serial data output when in register read mode. 10:5 reserved program to zero. 4rfup rf pll update rate (rf1 vco only). 0 = 200 khz update rate (receive gsm modes). 1 = 100 khz update rate (receive dcs and pcs modes). note: this bit is set to 1 when register 20h d[17:16] = 01 b or 10 b (dcs 1800 or pcs 1900 receive modes) and is set to 0 when d[17:16] = 00 b or 11 b (gsm 850 or gsm 900 modes). 3div2 input clock frequency. 0 = no divider. xin = 13 mhz. 1 = divide xin by 2. xin = 26 mhz. 2:1 reserved program to zero. 0 reserved program to one.
aero rev. 1.4 37 register 32h. powerdown (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000000000pdibpdrb bit name function 17:2 reserved program to zero. 1pdib powerdown if pll. 0 = if synthesizer powered down. 1 = if synthesizer powered up when the pdn pin is high. notes: 1. the if pll is only used in transm it mode. powerdown for receive mode. 2. this bit is set to 0 when register 20h is written (receive mode). 3. this bit is set to 1 when register 23h is written (transmit mode). 0 pdrb powerdown rf pll. 0 = rf synthesizer powered down. 1 = rf synthesizer powered up when the pdn pin is high. notes: 1. this bit is set to 1 when register 20h is written (receive mode). 2. this bit is set to 1 when register 23h is written (transmit mode). register 33h. rf1 n divider (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n rf1 [15:0] bit name function 17:16 reserved program to zero. 15:0 n rf1 [15:0] n divider for rf pll (rf1 vco). used for receive mode. register 34h. rf2 n divider (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n rf2 [15:0] bit name function 17:16 reserved program to zero. 15:0 n rf2 [15:0] n divider for rf pll (rf2 vco). used for transmit mode.
aero 38 rev. 1.4 register 35h. if n divider (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n if [15:0] bit name function 17:16 reserved program to zero. 15:0 n if [15:0] n divider for if synthesizer. used for transmit mode. register 3ah. reserved (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000001001 bit name function 17:4 reserved program to zero. 3 reserved program to one. 2:1 reserved program to zero. 0 reserved program to one. register 3eh. reserved (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000001111 bit name function 17:4 reserved program to zero. 3:0 reserved program to one.
aero rev. 1.4 39 register 3fh. reserved (si4133t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000010000 bit name function 17:5 reserved program to zero. 4 reserved program to one. 3:0 reserved program to zero.
aero 40 rev. 1.4 6. pin descriptions: si4200-g-gm pin number(s) name description 1, 2 ion, iop data output to si4201 (differential). 3, 4 ckn, ckp clock input from si4201 (differential). 5, 6 txip, txin transmit i input (differential). 7, 8 txqp, txqn transmit q input (differential). 9, 10 iflop, iflon iflo input from si4133t (differential). 11, 27, 30, gnd pad gnd ground. connect to ground plane on pcb. 12, 13 rflop, rflon rflo input from si4133t (differential). 14, 23, 26, 32 vdd supply voltage. 15, 16 diag2, diag1 d iagnostic output. can be used as digital outputs to control antenna switch functions. 17, 18 rfipp, rfipn pcs lna input (differential). use for pcs 1900 band. 19, 20 rfidp, rfidn dcs ln a input (differential). use for dcs 1800 band. 21, 22 rfigp, rfign gsm lna input (differential). used for gsm 850 or e-gsm 900 bands. 24 rfod dcs and pcs transmit output to power amplifier. used for dcs 1800 and pcs 1900 bands. 25 rfog gsm transmit outp ut to power amplifier. used for gsm 850 and e-gsm 900 bands. 28, 29 nc these pins should be left disconnected. 31 pdn powerdown input (active low). gnd pad 1 2 3 25 26 27 28 29 30 31 32 ion iop txqn txqp ckn ckp txin txip iflop iflon gnd rflop rflon vdd diag2 diag1 vdd pdn gnd nc nc gnd vdd rfog rfidp rfidn rfipp rfipn rfigp rfign vdd rfod 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8 top view
aero rev. 1.4 41 7. pin descriptions: si4200db-bm pin number(s) name description 1, 2 ion, iop data output to si4201 (differential). 3, 4 ckn, ckp clock input from si4201 (differential). 5, 6 txip, txin transmit i input (differential). 7, 8 txqp, txqn transmit q input (differential). 9, 10 iflop, iflon iflo input from si4133t (differential). 11, 19, 20, 27, 30, gnd pad gnd ground. connect to ground plane on pcb. 12, 13 rflop, rflon rflo input from si4133t (differential). 14, 23, 26, 32 vdd supply voltage. 15, 16 diag2, diag1 d iagnostic output. can be used as digital outputs to control antenna switch functions. 17, 18 rfipp, rfipn pcs lna input (differential). use for dcs 1800 or pcs 1900 bands. 21, 22 rfigp, rfign gsm lna input (differential). used for gsm 850 or e-gsm 900 bands. 24 rfod dcs and pcs transmit output to power amplifier. used for dcs 1800 and pcs 1900 bands. 25 rfog gsm transmit outp ut to power amplifier. used for gsm 850 and e-gsm 900 bands. 28, 29 nc these pins should be left disconnected. 31 pdn powerdown input (active low). gnd pad 1 2 3 25 26 27 28 29 30 31 32 ion iop txqn txqp ckn ckp txin txip iflop iflon gnd rflop rflon vdd diag2 diag1 vdd pdn gnd nc nc gnd vdd rfog gnd gnd rfipp rfipn rfigp rfign vdd rfod 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8 top view
aero 42 rev. 1.4 8. pin descriptions: si4201-bm pin number(s) name description 1, 8, gnd pad gnd ground. connect to ground plane on pcb. 2, 3 rxqp, rxqn receive q output (differential). 4, 5 rxip, rxin receive i output (differential). 6, 20 vdd supply voltage. 7 xin reference frequency input from crystal oscillator. 9, 10 ckp, ckn clock output to si4200 (differential). 11, 12 iop, ion data input from si4200 (differential). 13 xen xout pin enable 14 pdn powerdown input (active low). 15 sdo serial data output. 16 sen serial enable input (active low). 17 sclk serial clock input. 18 sdi serial data input. 19 xout clock output to baseband. top view gnd pad 1 2 3 16 17 18 19 20 gnd rxqp rxqn rxip rxin vdd xin gnd ckp ckn vdd xout sdi sclk sen iop ion xen pdn sdo 11 12 13 14 15 6 7 8 9 10 4 5
aero rev. 1.4 43 9. pin descriptions: SI4133T-BM pin number(s) name description 1, 4, 6, 8, 14, 15, 18, 21, 22, gnd pad gnd ground. connect to ground plane on pcb. 2, 3 iflb, ifla tuning inductor connection for if vco. 5, 25, 28 vdd supply voltage. 7 xin reference frequency input from crystal oscillator. 9pdn powerdown input (active low). 10 sdo serial data output. 11 sen serial enable input (active low). 12 sclk serial clock input. 13 sdi serial data input. 16, 17 rfld, rflc tuning inductor connection for rf2 vco. 19, 20 rflb, rfla tuning inductor connection for rf1 vco. 23, 24 rflon, rflop rf pll output to si4200 (differential). 26, 27 iflon, iflop if pll output to si4200 (differential). gnd pad 1 2 3 22 23 24 25 26 27 28 gnd iflb xin gnd ifla gnd vdd gnd pdn sdo sen sclk sdi gnd vdd iflop iflon vdd rflop rflon gnd rflc gnd gnd rfld rflb rfla gnd 15 16 17 18 19 20 21 8 9 10 11 12 13 14 4 5 6 7 top view
aero 44 rev. 1.4 10. ordering guide part number description package type operating temperature si4200-g-gm tri-band transceiver gsm 850 or e-gsm 900, dcs 1800, pcs 1900 qfn pb-free* ?20 to 85 c si4200db-bm dual-band aero transceiver gsm 850/pcs 1900 or e-gsm 900/dcs 1800 qfn* ?20 to 85 c si4200db-gm dual-band aero transceiver gsm 850/pcs 1900 or e-gsm 900/dcs 1800 qfn pb-free* ?20 to 85 c si4201-bm universal baseband interface qfn* ?20 to 85 c si4201-gm universal baseband interface qfn pb-free* ?20 to 85 c SI4133T-BM dual rf synthesizer qfn* ?20 to 85 c si4133t-gm dual rf synthesizer qfn pb-free* ?20 to 85 c *note: add an ?r? at the end of the device to denote tape and reel option; 2500 quantity per reel.
aero rev. 1.4 45 11. package outline: si4200-g-gm and si4200db-bm figure 18 illustrates the package details for the si4200-g -gm and the si4200db-bm. table 11 lists the values for the dimensions shown in the illustration. figure 18. 32-pin quad flat no-lead package (qfn) table 11. package dimensions symbol millimeters symbol millimeters min nom max min nom max a ? 0.85 0.90 d1, e1 4.75 bsc a1 0.00 0.01 0.05 d2, e2 3.15 3.30 3.45 a2 ? 0.65 0.70 e 0.50 bsc a3 0.20 ref. ??12 b 0.18 0.23 0.30 l 0.30 0.40 0.50 d, e 5.00 bsc notes: 1. dimensioning and tolerances c onform to asme y14.5m. - 1994 2. package warpage max 0.05 mm. 3. ?b? applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal tip. 4. the package weight is approximately 68 mg. 5. the mold compound for this package has a flammability rating of ul94-v0 with an oxygen index of 28 minimum/54 typical. 6. the recommended reflow profile for this package is de fined by the jedec-020b small body specification. 32 bottom view 1 1 e2 d2 2 3 top view side view a a1 a2 a3 2 3 pin1 id 0.50 dia. b 32 b e l pin1 id 0.20 r. e e e1 d d1
aero 46 rev. 1.4 12. package outline: si4201-bm figure 19 illustrates the package details for the si4201-bm. table 12 lists the values for the dimensions shown in the illustration. figure 19. 20-pin quad flat no-lead package (qfn) table 12. package dimensions symbol millimeters symbol millimeters min nom max min nom max a ? 0.85 0.90 d1, e1 3.75 bsc a1 0.00 0.01 0.05 d2, e2 1.95 2.10 2.25 a2 ? 0.65 0.70 e 0.50 bsc a3 0.20 ref. ??12 b 0.18 0.23 0.30 l 0.50 0.60 0.75 d, e 4.00 bsc notes: 1. dimensioning and tolerances c onform to asme y14.5m. - 1994 2. package warpage max 0.05 mm. 3. ?b? applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal tip. 4. the package weight is approximately 42 mg. 5. the mold compound for this package has a flammability rating of ul94-v0 with an oxygen index of 28 minimum/54 typical. 6. the recommended reflow profile for this package is de fined by the jedec-020b small body specification. 20 bottom view 1 1 e2 d2 2 3 top view side view a a1 a2 a3 2 3 e e1 pin1 id 0.50 dia. d b 20 d1 b e e l
aero rev. 1.4 47 13. package outline: SI4133T-BM figure 20 illustrates the package details for the SI4133T-BM. table 13 lists th e values for the dimensions shown in the illustration. figure 20. 28-pin quad flat no-lead package (qfn) table 13. package dimensions symbol millimeters symbol millimeters min nom max min nom max a ? 0.85 0.90 d1, e1 4.75 bsc a1 0.00 0.01 0.05 d2, e2 2.55 2.70 2.85 a2 ? 0.65 0.70 e 0.50 bsc a3 0.20 ref. ??12 b 0.18 0.23 0.30 l 0.50 0.60 0.75 d, e 5.00 bsc notes: 1. dimensioning and tolerances c onform to asme y14.5m. - 1994 2. package warpage max 0.05 mm. 3. ?b? applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal tip. 4. package weight is approximately 66 mg. 5. the mold compound for this package has a flammability rating of ul94-v0 with an oxygen index of 28 minimum/54 typical. 6. the recommended reflow profile for this package is de fined by the jedec-020b small body specification. 28 bottom view 1 1 e2 d2 2 3 top view side view a a1 a2 a3 2 3 e e1 pin1 id 0.50 dia. d b 28 d1 b e e l pin1 id 0.20 r.
aero 48 rev. 1.4 d ocument c hange l ist revision 1.2 to revision 1.3 this document corresponds to the following: si4200db revision e (dual band lna) and si4200 revision f (triple band lna) si4201 revision c si4133t revisions b and c "10. ordering guide" on page 44 updated to include lead-free ordering option. "11. package outline: si4200-g-gm and si4200db- bm" on page 45 updated d2,e2 dimensions. updated device weight. added notes 5 and 6. "12. package outline: si4201-bm" on page 46 updated l dimension. updated device weight. added notes 5 and 6. "13. package outline: SI4133T-BM" on page 47 updated d2,e2 dimensions. updated device weight. added notes 5 and 6. revision 1.3 to revision 1.4 updated "10. ordering guide" on page 44 to include the si4200-g-gm.
aero rev. 1.4 49 n otes :
aero 50 rev. 1.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, texas 78701 tel:1+ (512) 416-8500 fax:1+ (512) 416-9669 toll free:1+ (877) 444-3032 email: aeroinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and aero are trademarks of silicon laboratories inc. other products or brand names mentioned herein are tradema rks or registered trademarks of their respective holder the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon labo ratories assumes no responsib ility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further not ice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of t he application or use of any produc t or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental da mages. silicon laboratories products are not designed, intended, or authorized for use in applica- tions intended to support or sustain life, or for any other appl ication in which the failure of the silicon laboratories produc t could create a situation where personal injury or death may occur. should bu yer purchase or use silicon laboratories products for any such uni ntended or unauthorized application, buye r shall indemnify and hold sili con laboratories harmless against all claims and damages.

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